Gallium Arsenide: Why This Compound?
Silicon is everywhere — so why do VCSEL makers pay 10× more for GaAs wafers? The answer is physics.
Direct Bandgap
In a direct bandgap material, electrons fall straight from the conduction band to the valence band and release a photon. In silicon (indirect bandgap), that transition requires a phonon (crystal vibration) — making silicon almost useless as a light emitter. GaAs's direct 1.42 eV bandgap means nearly every electron-hole recombination produces a photon — laser-grade internal quantum efficiency > 90%.
Electron Mobility
Electrons move through GaAs at ~8,500 cm²/V·s — 6× faster than in silicon (1,400 cm²/V·s). Faster electrons mean VCSELs can switch on and off at 25–112 Gbps speeds, essential for 400G/800G optical transceivers. At these speeds, silicon devices simply cannot keep up.
Lattice Engineering
GaAs's crystal lattice parameter (5.653 Å) closely matches those of AlGaAs and InGaAs — the materials used for the DBR mirrors and quantum wells. This lattice matching allows near-perfect crystalline interfaces between layers with < 0.01% mismatch. Mismatched interfaces introduce dislocations that non-radiatively kill photons — destroying laser performance.
Gallium (melting point 29.8°C — it melts in your hand) and arsenic (toxic solid, sublimes to As₄ vapour at 887°C) are sealed together in a quartz ampoule under inert atmosphere. Heating drives the reaction to form polycrystalline GaAs — a random jumble of crystals. This must then be re-melted and re-grown as a single perfect crystal. Arsenic's toxicity requires sealed, negative-pressure facilities with scrubbed exhaust.
Growing a Perfect GaAs Crystal
Polycrystalline GaAs is useless for chips. Every atom must be in the right place — aligned to a single crystalline lattice across a 150mm cylinder.
Polycrystal GaAs is melted at 1,238°C in a PBN crucible inside an inert N₂ pressure vessel. Boron oxide (B₂O₃) floats on the melt as a liquid glass — trapping arsenic vapour and preventing stoichiometry loss.
A <5mm seed crystal of known crystallographic orientation (typically [100] direction) is touched to the melt surface. Its lattice structure templates the growing solid — forcing all new atoms into the same alignment.
The seed is slowly pulled upward at 3–12 mm/hour while rotating at 5–20 RPM. The melt-solid interface moves with the pull — atoms solidify on the seed's lattice. The necked shoulder prevents dislocations propagating from the seed into the body.
Finished ingots (75–150mm diameter, 200–300mm long) are tested by X-ray diffraction to confirm crystal orientation, etch pit density (EPD < 500/cm² for VCSEL grade), and carrier concentration (n or p-type, 10¹⁶–10¹⁸ cm⁻³).
8 Steps from Wafer to Working VCSEL
Each step in the fab is irreversible. A mistake at step 5 destroys all the work from steps 1–4 — which is why semiconductor fabs operate in ISO Class 1 cleanrooms.
Epitaxy (MOCVD)
The GaAs wafer is loaded into a MOCVD (Metal-Organic Chemical Vapour Deposition) reactor — a stainless-steel chamber the size of a filing cabinet. Inside, metal-organic precursor gases (trimethylgallium, trimethylaluminium, trimethylindium) and arsine gas flow over the rotating heated wafer at 600–750°C. The gases decompose and deposit atoms one monolayer at a time, building up the precise semiconductor stack needed for lasing.
This process builds 50–65 distinct layers totalling just 5–8 micrometres (thinner than a human hair, which is ~70 µm). Precision is sub-angstrom — one wrong monolayer ruins the device. Growth rates are ~1 µm/hour, so a full VCSEL stack takes 6–10 hours.
Visual: Mesa Etching (Photolithography + ICP-RIE)
Visual: Oxide Aperture Formation
Visual: Completed VCSEL Structure (Passivation + Contacts + Laser Output)
Visual: On-Wafer Probe Testing — The VCSEL Advantage
Visual: Dicing, Packaging & Final Products
Full Manufacturing Swimlane
Every actor, every step, every handoff — from ore in the ground to laser light in your phone.
Cleanroom Class
VCSEL fabs operate in ISO Class 1–3 cleanrooms (< 10 particles > 0.1µm per m³). Outside air has ~35 million particles per m³. A single dust particle on a mesa can short-circuit a laser. Workers wear full-body bunny suits, gloves, and face shields at all times.
Capital Cost
A full MOCVD reactor costs $3–8 million. A complete GaAs VCSEL fab requires $500M–$1.5B in equipment. That's why only ~8 companies globally (Lumentum, Coherent/II-VI, ams OSRAM, Broadcom, WIN Semi, etc.) have full in-house VCSEL manufacturing capability.
Why GaAs not InP?
Indium Phosphide (InP) enables 1310/1550nm VCSELs (telecom wavelengths) but is mechanically fragile, more expensive, and harder to process in 100mm+ wafers. GaAs at 850nm dominates consumer and datacenter VCSEL markets. InP VCSELs are used for long-haul telecom and eye-safe LiDAR.
Qualification & Reliability
Automotive VCSELs must pass AEC-Q102: 1000 hours at 85°C/85% humidity, thermal shock -55°C to +125°C, 100G vibration, and ESD tests. Consumer VCSELs undergo JEDEC JESD22 qualification. Expected MTBF: >200,000 hours (>22 years) — longer than the device they're embedded in.
Manufacturing Jargon Decoded
Metal-Organic Chemical Vapour Deposition — deposits atom-by-atom semiconductor layers from gas-phase metal-organic precursors.
Distributed Bragg Reflector — semiconductor mirror made of alternating quarter-wavelength layers with >99.9% reflectance.
Inductively Coupled Plasma Reactive Ion Etching — uses ionised gas plasma to etch semiconductor with near-perfect vertical walls.
Liquid Encapsulated Czochralski / Vertical Gradient Freeze — two methods to grow single-crystal GaAs ingots from melt.
Chemical Mechanical Polishing — uses slurry + pad to produce wafer surfaces flat to < 0.2 nm roughness (Ra).
Plasma-Enhanced CVD — deposits dielectric films (SiO₂, Si₃N₄) at low temperature using plasma activation.
UV-sensitive polymer spun onto wafer; exposed areas change solubility, enabling pattern transfer from mask to semiconductor.
Light-Current-Voltage characteristic — the definitive test measuring lasing threshold, efficiency, and operating voltage of each die.
Ultra-thin (< 10 nm) semiconductor layer where quantum confinement forces electrons and holes to recombine and emit photons efficiently.
Central unoxidised circle in the AlAs layer (3–10 µm) that confines electrical current into the active region.
EPD — count of crystalline defects per cm² in the GaAs wafer. VCSEL-grade requires < 500/cm².
Difference in crystal spacing between adjacent semiconductor layers. >0.1% mismatch causes dislocations that kill laser performance.
n-type ohmic contact metallurgy — gold-germanium alloy makes ohmic contact to n-type GaAs after 420°C anneal.
Cutting the processed wafer into individual die using diamond blade saw or stealth (laser) dicing system.
Packaging where chip is flipped face-down and solder-bumped directly onto a substrate — enables co-packaged optics (CPO).